1. Field of the Invention
The present invention relates to a method and circuitry for supplying a system clock signal to an integrated circuit (or internal circuit) of a semiconductor device, such as a microcomputer, including a built-in phase-locked loop (i.e., PLL) frequency multiplier.
2. Description of the Prior Art
Referring now to FIG. 9, there is illustrated a schematic circuit diagram showing the structure of prior art clock supply circuitry including a PLL frequency multiplier, the clock supply circuitry being built in a semiconductor device. In the figure, reference numeral 10 denotes the semiconductor device including the prior art clock supply circuitry, numeral 20 denotes the PLL frequency multiplier for generating a frequency-multiplied clock signal from an input clock signal, the frequency-multiplied clock signal having a frequency that is an integral multiple of the frequency of the input clock signal, numeral 30 denotes an oscillator driving circuit for driving an external oscillator connected between an input terminal Xin and an output terminal Xout, numeral 40 denotes a PLL output supply circuit for delivering the frequency-multiplied clock signal from the PLL frequency multiplier 20 as a system clock signal to an integrated circuit 50 after counting a pulse of the input clock signal applied to the PLL frequency multiplier 20 a predetermined number of times, when returning the clock supply circuitry from a stop state in which it is stopping the supply of the system clock to the integrated circuit 50 to its original state or clock supply state in which it is supplying the system clock signal to the integrated circuit 50, numeral 401 denotes a counter for reloading a maximum count value thereinto and resetting its output so as. to put its output at a xe2x80x9cLowxe2x80x9d level every time a control signal or stop instruction signal applied thereto becomes a xe2x80x9cHighxe2x80x9d level, and for starting counting down pulses of the input clock signal applied to the PLL frequency multiplier 20 and for furnishing an output at a xe2x80x9cHighxe2x80x9d level when it underflows, numeral 402 denotes an SR flip-flop having an S terminal connected to an output terminal of the counter 401 and an R terminal for receiving the stop instruction signal, numeral 403 denotes a switch having a control terminal connected to a Q terminal of the SR flip-flop 402, numeral 60 denotes an SR flip-flop having an S terminal for receiving a recovery instruction signal and an R terminal for receiving the stop instruction signal, and numeral 70 denotes a switch having a control terminal connected to a Q terminal of the SR flip-flop 60. The system clock signal that is the output (or PLL output) of the PLL frequency multiplier 20 can be applied, by way of the switch 403, to the integrated circuit 50.
In operation, the counter 401 reloads the maximum count value thereinto and resets its output so as to put its output at a xe2x80x9cLowxe2x80x9d level every time the stop instruction signal applied to a control terminal thereof becomes a xe2x80x9cHighxe2x80x9d level. When the Q output of the SR flip-flop 402 becomes a xe2x80x9cHighxe2x80x9d level, the switch 403 is brought into conduction or placed to the ON position. In contrast, when the Q output of the SR flip-flop 402 becomes a xe2x80x9cLowxe2x80x9d level, the switch 403 is brought out of conduction or placed to the OFF position. Similarly, when the Q output of the SR flip-flop 60 becomes a xe2x80x9cHighxe2x80x9d level, the switch 70 is brought into conduction or placed to the ON position. In contrast, when the Q output of the SR flip-flop 60 becomes a xe2x80x9cLowxe2x80x9d level, the switch 70 is brought out of conduction or placed to the OFF position. A signal passing through each of the two switches 403 and 70 has either a xe2x80x9cHighxe2x80x9d level or a xe2x80x9cLowxe2x80x9d level according to whether a corresponding input signal has a voltage greater than or equal to or less than a threshold value.
A clock generating device 11 as shown in FIG. 10 can be connected to the input terminal Xin of FIG. 9. As an alternative, an external oscillator 12 as shown in FIG. 11 can be connected between the input terminal Xin and the output terminal Xout.
First, a description will be made as to the operation of the clock supply circuitry when a clock generating device 11 is connected to the input terminal Xin, as shown in FIG. 10. While the clock supply circuitry is placed in a clock supply stopping state, i.e., stop state in which it is stopping the supply of the system clock signal to the integrated circuit 50, both the PLL frequency multiplier 20 and the oscillator driving circuit 30 are at a stand still. When the clock supply circuitry is brought to the stop state, the stop instruction signal becomes a xe2x80x9cHighxe2x80x9d level and the recovery instruction signal becomes a xe2x80x9cLowxe2x80x9d level. As a result, the SR flip-flop 60 is reset and its Q output becomes a xe2x80x9cLowxe2x80x9d level, and therefore the switch 70 is brought out of condition. When the stop instruction signal becomes a xe2x80x9cHighxe2x80x9d level, the counter 401 reloads the maximum count value thereinto and resets its output so as to put its output at a xe2x80x9cLowxe2x80x9d level, and then starts counting down pulses of the input clock signal applied to the PLL frequency multiplier 20. In this case, since no clock pulse is applied to the counter 401, the counter 401 keeps its count value at the maximum count value. Furthermore, the SR flip-flop 402 is also reset and its Q output becomes a xe2x80x9cLowxe2x80x9d level, and therefore the switch 403 is brought out of condition. As a result, the output terminal of the PLL frequency multiplier 20 is disconnected from the integrated circuit 50.
When the recovery instruction signal becomes a xe2x80x9cHighxe2x80x9d level while the clock supply circuitry is placed in the stop state, the semiconductor device 10 starts a recovery process of canceling the stopping of the supply of the system clock signal to the integrated circuit. First, the PLL frequency multiplier 20 and the oscillator driving circuit 30 start working. Since the stop instruction signal simultaneously becomes a xe2x80x9cLowxe2x80x9d level, the SR flip-flop 60 is set and its Q output becomes a xe2x80x9cHighxe2x80x9d level, and therefore the switch 70 is brought into condition. Although the PLL frequency multiplier 20 receives a stable clock signal from the clock generating device 11, as shown in FIG. 12, the PLL output supply circuit 40 cannot supply the PLL output to the integrated circuit 50 immediately after it receives the frequency-multiplied clock signal because some interval of time is required for the frequency-multiplied clock signal (or PLL output) from the PLL frequency multiplier 20 to become stable. In order to keep the switch 403 being in the OFF position until the PLL output becomes stable, the counter 401 of the PLL output supply circuit 40 counts down pulses of the input clock signal from the maximum count value. When the counter 401 underflows, it furnishes an output at a xe2x80x9cHighxe2x80x9d level. As a result, the SR flip-flop 402 is set and the switch 403 is brought into conduction or placed to the ON position, and therefore the frequency-multiplied clock signal from the PLL frequency multiplier 20 is supplied as the system clock signal to the integrated circuit 50. The recovery process is thus completed. The length of time that elapses until the counter 401 underflows after the recovery process is started and the input clock signal is then applied to the counter 401 corresponds to the maximum count value set to the counter 401. The maximum count value is predetermined based on the simulated or measured longest time required for the PLL output to become stable so that the maximum count value allows for a margin. The longest time can be determined by estimating the time required for the output of the PLL frequency multiplier to become stable, and either performing circuit simulations in consideration of variations in ambient temperature and power supply voltage or performing experiments under a variety of operating conditions. As shown in FIG. 12, the PLL output supply circuit 40 brings the switch 403 into conduction at the expiration of about the margin after the PLL output becomes stable.
Next, a description will be made as to the operation of the clock supply circuitry when an external oscillator 12 is connected between the input terminal Xin and the output terminal Xout, as shown in FIG. 11. As in the case that the clock generating device 11 is connected to the input terminal Xin, as shown in FIG. 10, the PLL output supply circuit 40 measures the time that elapses before the frequency-multiplied clock signal from the PLL frequency multiplier 20 becomes stable using the counter 401 without supplying the PLL output to the integrated circuit 50 immediately after receiving the frequency-multiplied clock signal because some interval of time is required for the frequency-multiplied clock signal to become stable. When the counter 401 counts down pulses of the input clock signal from the maximum count value and then underflows, it furnishes an output at a xe2x80x9cHighxe2x80x9d level to set the SR flip-flop 402 and hence bring the switch 403 into conduction. As a result, the frequency-multiplied clock signal from the PLL frequency multiplier 20 is supplied as the system clock signal to the integrated circuit 50. The recovery process is thus completed.
Unlike the case where the clock generating device 11 is connected to the input terminal Xin, as previously explained, the oscillation of the external oscillator 12 and hence the waveform of the input clock signal are unstable immediately after the recovery process is started, as shown in FIG. 13. Nevertheless, the input clock signal (or PLL input) having an unstable waveform is furnished to the PLL frequency multiplier 20. Therefore, in order to make the frequency-multiplied clock signal that is the output of the PLL frequency multiplier 20 become stable, the oscillation of the external oscillator 12 needs to become stable first. In other words, the input clock signal applied to the input terminal Xin needs to become stable first.
In this case, the maximum count value set to the counter 401 is predetermined based on the simulated or measured longest time required for the PLL output to become stable so that the maximum count value allows for a margin. The longest time can be determined by estimating the time required for the external oscillator 12 to become stable and the time required for the output of the PLL frequency multiplier 20 to become stable, and either performing circuit simulations in consideration of variations in ambient temperature and power supply voltage or performing experiments under a variety of operating conditions. As shown in FIG. 13, the PLL output supply circuit 40 brings the switch 403 into conduction at the expiration of about the margin after the input clock signal becomes stable and, after that, the PLL output becomes stable.
A problem with prior art clock supply circuitry constructed as above is that the maximum count value set to the counter 401 has to be predetermined so that the maximum count value allows for a margin, by estimating the time required for the output of the PLL frequency multiplier to become stable, further estimating the time required for the external oscillator to become stable when needed, and evaluating the longest time required for the PLL output to become stable by simulation or experiment in consideration of variations in ambient temperature and power supply voltage, and therefore additional time and effort must be expended on the determination of the maximum count value.
Another problem is that since no mechanism for determining whether the output of the PLL frequency multiplier becomes stable is provided, the maximum count value set to the counter corresponds to a length of time longer than necessary and therefore it takes much time for the system clock to be delivered to the internal circuit, such as an integrated circuit, after the recovery process is started, so that the semiconductor device cannot perform processes at expected times, and, even though the PLL frequency multiplier does not become stable, the PLL frequency multiplier can furnish its output to the internal circuit and hence the internal circuit may run away.
The present invention is proposed to solve the above problems. It is therefore an object of the present invention to provide a clock supply method and circuitry capable of supplying a system clock signal to an internal circuit as soon as possible after a recovery process of canceling the stopping of the supply of the system clock signal to the internal circuit is started so as to make the internal circuit work, thus preventing the internal circuit from running away.
In accordance with one aspect of the present invention, there is provided a method of supplying a system clock signal to an internal circuit, comprising the steps of: when returning to a clock supply state in which a phase-locked loop or PLL frequency multiplier is generating a frequency-multiplied clock signal from an input clock signal and supplying the frequency-multiplied clock signal to the internal circuit, the frequency-multiplied clock signal having a frequency that is an integral multiple of the frequency of the input clock signal, from a clock supply stopping state in which the PLL frequency multiplier is stopping the generation of the frequency-multiplied clock signal, determining whether the frequency-multiplied clock signal from the PLL frequency multiplier becomes stable; and supplying the frequency-multiplied clock signal as the system clock signal to the internal circuit after it is determined that the frequency-multiplied clock signal becomes stable.
Preferably, the determining step is the step of determining whether signals generated by the PLL frequency multiplier for controlling the frequency of the frequency-multiplied clock signal indicate that the frequency of the frequency-multiplied clock signal becomes stable, and, when the signals indicate that the frequency of the frequency-multiplied clock signal becomes stable, the frequency-multiplied clock signal is supplied as the system clock signal to the internal circuit.
In accordance with another aspect of the present invention, there is provided clock supply circuitry for supplying a system clock signal to an internal circuit, the circuitry comprising: a phase-locked loop or PLL frequency multiplier for generating a frequency-multiplied clock signal having a frequency that is an integral multiple of the frequency of an input clock signal; and a PLL output stability detecting circuit for determining whether the frequency-multiplied clock signal from the PLL frequency multiplier becomes stable when the clock supply circuitry is made to return from a clock supply stopping state in which the PLL frequency multiplier is stopping the generation of the frequency-multiplied clock signal to a clock supply state in which the PLL frequency multiplier is generating and supplying the frequency-multiplied clock signal to the internal circuit, and for supplying the frequency-multiplied clock signal from the PLL frequency multiplier as the system clock signal to the internal circuit after the PLL output stability detecting circuit determines that the frequency-multiplied clock signal becomes stable.
Preferably, the PLL output stability detecting circuit includes a switch disposed between an output terminal of the PLL frequency multiplier and the internal circuit, the switch being placed to ON position when the PLL output stability detecting circuit supplies the frequency-multiplied clock signal as the system clock signal to the internal circuit, and a control unit for placing the switch to the ON position when signals generated by the PLL frequency multiplier for controlling the frequency of the frequency-multiplied clock signal indicate that the frequency of the frequency-multiplied clock signal becomes stable when returning the clock supply circuitry from the clock supply stopping state to the clock supply state.
The PLL frequency multiplier can include a phase comparator for comparing a phase of the input clock signal with that of a frequency-divided clock signal, and for furnishing an XINFAST signal including a pulse having a duration corresponding to a phase difference between the phases of the input clock signal and the frequency-divided clock signal and a PLLFAST signal fixed at a certain level opposite to the level of the pulse of the XINFAST signal when the phase of the input clock signal leads that of the frequency-divided clock signal, for furnishing a PLLFAST signal including a pulse having a duration corresponding to a phase difference between the phases of the input clock signal and the frequency-divided clock signal and an XINFAST signal fixed at a certain level opposite to the level of the pulse of the PLLFAST signal when the phase of the input clock signal lags behind that of the frequency-divided clock signal, and for furnishing XINFAST and PLLFAST signals fixed at the certain level when the input clock signal is in phase with the frequency-divided clock signal. The PLL frequency multiplier can further include a charge pump for furnishing a pulse at a xe2x80x9cHighxe2x80x9d level having a duration corresponding to the pulse of the XINFAST signal when the phase of the input clock signal leads that of the frequency-divided clock signal, and for furnishing a pulse at a xe2x80x9cLowxe2x80x9d level having a duration corresponding to the pulse of the PLLFAST signal when the phase of the input clock signal lags behind that of the frequency-divided clock signal, a low-pass filter for converting the pulse from the charge pump into a DC voltage, a voltage-controlled oscillator for generating and furnishing the frequency-multiplied clock signal having a frequency corresponding to the DC voltage, and a frequency divider for dividing the frequency of the frequency-multiplied clock signal so as to generate the frequency-divided clock signal having a frequency that is an integral submultiple of that of the frequency-multiplied clock signal.
Preferably, the control unit includes a logical circuit for receiving the XINFAST and PLLFAST signals from the PLL frequency multiplier and for generating a control signal asserted when the XINFAST and PLLFAST signals are at different or opposite levels; a counter, responsive to the control signal from the logical circuit, for reloading a maximum count value thereinto, resetting its output to a xe2x80x9cLowxe2x80x9d level, and starting counting down the input clock signal from the maximum count value, and for furnishing a signal at a xe2x80x9cHighxe2x80x9d level when it underflows, and an SR flip-flop having an S terminal for receiving an output of the counter, an R terminal for receiving a stop instruction signal that becomes a xe2x80x9cHighxe2x80x9d level when the clock supply circuitry stops the supply of the system clock signal to the internal circuit, and a Q terminal via which the SR flip-flop furnishes a switching signal for switching the switch between ON and OFF positions.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.